Control Unit for Parallel Embedded System

New integration methodologies as IP reuse have become more and more popular since few years. These methodologies represent an opportunity to reduce the gap between the integration capacities and the ability of the designers to develop complex systems. SOC (System On Chip), that are composed of different heterogeneous cores, have taken benefit of these methodologies. Recent SOCs are usually Globally Asynchronous and Locally Synchronous and exploit a lot of parallelism. Up to now, research efforts have mainly been focused on the definition of new communication and processing primitives. Unfortunately, control mechanisms have not evolved as fast as the rest of the system. Besides, these devices are usually organized around a microprocessor supporting an operating system managing the execution of the different tasks on the processing primitives and their communications. We propose in this paper a hardware solution to manage tasks and communication in such parallel systems. This controller focus on the implementation of Petri nets and has the property to be reconfigurable and to self-manage its configurations. Physical implementation of this component has been done in 0.13μm technology.